Six-core Intel processors coming THIS year

Advancing its architecture at what mostindependent observers would now agree is a breakneck pace, Inteloffered further details today on how soon it would begin phasing outthe Core Microarchitecture it introduced in the summer of 2006.
Withthe second phase of its 45 nm generation microprocessors -- what itcalls "tock," using a metaphor that drives rival AMD mad -- Intel willmove to a processor design that utilizes scalable cores, from two all the way to eight, it will introduce anothernew microarchitecture for processing instructions, and it will phaseout the front-side bus as a component of its architecture. We've knownthese facts based on bits and pieces of information compiled from Intelhints over the past six months. Now we know this as absolute fact,confirmed by senior vice president Pat Gelsinger during a specialpresentation this morning.

Now we know when it will all happen forcertain. The six-core Dunnington server CPU platform using Penrynarchitecture (the "tick" generation of 45 nm), with 16 MB of L3 cache,goes into production as soon as this summer. The 45 nm Nehalemarchitecture ("tock") enters production in the fourth quarter of thisyear. That will be the beginning of the end of the era of Intel x86computers with a front-side bus (a separate circuit linking the CPU tomemory, with a dedicated clock).
And Itanium lives on, as thecompany's new Tukwila architecture will carry the intrinsicallymulti-threaded instruction set into datacenters and mainframereplacements, with six cores sharing 30 MB of cache.
But it willbe Nehalem that is expected to provide one very thunderous "tock." Onekey feature that literally creates an entirely new dimension toparallelism will be simultaneous multithreading (SMT): theability for each core to process two threads at a time, not alternatelylike hyperthreading but truthfully at the same time.
An updated Nehalem white paper today (PDF available here)describes SMT as "a more energy efficient means of increasingperformance for multi-threaded workloads. The next generationmicroarchitecture's SMT capability enables running two simultaneousthreads per core -- an amazing eight simultaneous threads per quad-coreprocessor and 16 simultaneous threads for dual-processor quad-coredesigns."

Soa four-way quad-core Nehalem system may have to be quantified as "4 x 4x 2," in a designation that is sure to give a new source of headachesfor AMD. A few weeks ago, that company began gathering support for its first 45 nm generation,even though it won't yet feature AMD's version of thehigh-k-plus-metal-gate manufacturing technology it developed with IBM;that's being reserved for a future generation.
Meanwhile, one ofAMD's remaining design "edges" against Intel -- its Direct Connectmemory bus -- will no longer be an edge once Intel inaugurates itsQuickConnect architecture. Replacing the front-side bus will be a moredirect link that Intel now calls its "QuickPath Interconnect."
"A big advantage of the Intel QuickPath Interconnect is that it is point-to-point," reads a new white paper on the subject (PDF available here)."There is no single bus that all the processors must use and contendwith each other to reach memory and I/O. It also improves scalability,eliminating the competition between processors for bus bandwidth.Coupled with Intel's great cache memory, this technological achievementwill enable the performance of servers and workstations to take anotherleap forward."

Thefirst TPC benchmarks for the "tick" generation of Penryn architectureactually delivered a bit more performance than even independentobservers were expecting. No explicit performance data or projectionsfor Nehalem were released today, though the early word on the street isto plan not to use the word "astounding" too many times in oneparagraph.