Intel's new Bus architecture called "CSI"

QUOTE:

posted 2:05pm EST Thu Mar 03 2005 - submitted by Nicholas G. Lesniewski-Laas
BLURB

Intel's current shared bus architecture and off-chip memory access scheme have been outdated for years now, but in the next few years Intel promises to update its bus architecture.

The proposal put forth by Intel is called CSI, or Common Serial Interconnect, and should sport similar features to AMD's competing HyperTransport bus architecture. CSI is intended for use only in server-level Intel processors, namely the Itanium and Xeon class chips, but consumer-level chips, namely the Pentium and Pentium M lines, will be stuck with the old shared bus interface.

Intel is taking its time in designing the CSI architecture because along with it they need an on-chip memory controller to match the memory controller in AMD64 chips.

Even so, it's hard to imagine that Intel is unable to implement the bus and memory controller architectures before the end of 2007, over two years away.

And although using a common bus architecture for both its IA64 and x86-64 server chips will make the IA64 transition easier, it makes little sense to leave consumer-level Pentiums behind with their old and slow shared bus. Perhaps Intel is concerned that the transition to CSI within the next year would be overshadowed by the transition to dual-core processors scheduled for this year.

Intel is debating whether or not to release CSI as an open standard, and it will be interesting to see whether or not it can compete in the open market with the now mature and widely used HyperTransport.

http://www.geek.com/news/geeknews/2005Mar/...50303029422.htm